Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include integrated circuits. Integrated circuit fabrication usually involves multi-step processes that attempt to produce precise components. Many integrated circuit component fabrication processes involve complicated interactions that can have detrimental impacts on other components within the integrated circuit. It can be very difficult to achieve optimized results within requisite tolerances.
Semiconductor integrated circuit manufacturing efforts are usually complicated by ever increasing demands for greater functionality. More complicated circuits are usually required to satisfy the demand for greater functionality. For example, there is usually a proportional relationship between the number of components included in an integrated circuit and the functionality, integrated circuits with more components typically provide greater functionality. However, including more components within an integrated circuit often requires the components to be densely packed in relatively small areas and reliably packing a lot of components in relatively small areas of an IC is usually very difficult. For example, as devices scale down to a 32 nm node or less, manufacturing becomes increasingly challenging due to fundamental limits such as defining such small structures.
Some traditional approaches have attempted to achieve greater densities by utilizing three dimensional integrated circuits with multiple layers of devices. However, achieving high quality single crystal silicon for the upper layer devices has been a major roadblocks in the pursuit of three-dimensional multilayer device fabrication. Many integrated circuit devices rely upon very precise building blocks (e.g., a single crystal silicon region) for fabrication of reliable and proper operating devices. Conventional attempts at utilizing heat for annealing and creating single crystal regions is a second layer device region are difficult to implement because heat transfers to other layers are problematic. Attempts at fabricating the layers as separate dies and then combining them have also proved problematic due to lack of cost effective precise alignment techniques when mating the two separately fabricated portions.